1. Field of the Invention
The present invention relates to a method for correcting waveform data in digital signal modulation and, more particularly, to a method for correcting waveform data stored in a baseband generator of a digital modulator so as to reduce an accumulated error (The method is hereinafter referred to as the waveform data correction method.), and a baseband signal generator using data provided by the method.
2. Description of the Prior Art
FIG. 1 is a block diagram showing a baseband waveform generator in a quadrature modulation type digital FM modulator. In the figure, numeral 1 is a shift register (an element that can accommodate consecutive data) for storing a serial binary digital signal (input data). Numeral 2 is a waveform memory for storing waveform data obtained by quantizing a baseband waveform and outputting a waveform similar to the baseband waveform. Numeral 3 is a counter for counting a clock signal. Numeral 4 is an adder for adding the waveform data output from the waveform memory 2 to the output data from a latch circuit 5. The latch circuit 5 latches the output data from the adder 4 and supplies the data back to the adder 4. The adder 4 and the latch circuit 5 constitute an integrator that add up consecutively the waveform data coming out of the waveform memory 2. Numeral 6a is a COS-ROM for converting the output data from the adder 4 into an I signal (in-phase signal). Numeral 6b is a SIN-ROM for converting the output data from the adder 4 into a Q signal (quadrature-phase signal). Numerals 7a and 7b are D-A converters for converting the I signal and the Q signal into analog waveforms, respectively. Numerals 8a and 8b are low-pass filters (LPF) for shaping a waveform output from the respective D-A converters. Numerals 9a and 9b are respectively an I output and a Q output, being fed to the quadrature modulator (not shown in this figure).
In the setup described above, the waveform memory 2 stores a quantized baseband waveform as waveform data. As such, the waveform data contains a quantization error. As the waveform data from the waveform memory 2 are added up by the adder 4, the quantization errors involved are accumulated. To eliminate the accumulated quantization errors requires suitable arrangements for error correction. There is known a method in which the waveform data stored in the waveform memory 2 are previously corrected. FIG. 3 is a flowchart showing how this kind of correction is done.
What follows is a description of how the baseband generator works and how the waveform data is corrected thereby. First, the operation of the baseband generator is explained. Where the modulation process involves the so-called intersymbol interference, input data is stored in the shift register 1. A baseband waveform corresponding to all the patterns of the data stored in the shift register 1 is stored in the waveform memory 2 as quantized values obtained by sampling the baseband waveform at a rate of n times the bit rate. Thus a clock signal generated at the rate of n times the bit rate is counted by the n-based counter 3. Every time a counted value reaches n, the shift register 1 shifts the input data. The waveform memory 2 is arranged to output waveform data every time the counter 3 counts one clock pulse. The waveform data from the waveform memory 2 are added up consecutively, i.e., integrated, by the adder 4 and the latch circuit 5. In this manner, frequency information is converted to phase information. The phase information thus obtained is converted by the COS-ROM 6a and the SIN-ROM 6b into the I signal and Q signal for quadrature modulation. The two signals are then converted to analog signals by the D-A converters 7a and 7b. After waveform shaping by the LPF's 8a and 8b, the I output 9a and the Q output 9b are output as analog signals to a quadrature modulator.
FIG. 2 illustrates a typical relationship between a baseband waveform 10 and waveform data 11b. The waveform memory 2 outputs a quantized baseband waveform 11a corresponding to the baseband waveform 10. That is, the waveform data 11b is stored at an address in memory 2 specified by the value in the shift register 1 and by the value in the counter 3. In FIG. 2, it is assumed that sixteen items of waveform data 11b correspond to a single bit interval of input data 11c (i.e., n=16). In this case, the value obtained by the adder 4 adding up the sixteen items of waveform data 11b is so optimized as to fall within the width of one quantization step with respect to the value obtained by adding the sixteen sampled values. That is, sixteen items of waveform data 11b in a single bit interval of input data are arranged so that the added value of waveform data 11b keyed to the single bit interval has its error fall within one quantized step with respect to the baseband waveform. For example, adding up the sixteen items of waveform data 11b in FIG. 2 provides a value of 89. This value includes a quantization error with respect to the baseband waveform 10 which is within one quantization step.
As described above, as far as waveform data 11c in a single bit interval is concerned, it is relatively easy not to let the accumulated error from additions exceed the quantization step width. When waveform data 11c of multiple bit intervals is consecutively added, there is a possibility that the accumulated error may exceed the quantization step width. To eliminate the error simply requires correcting a number of waveform data items.
FIG. 3 is a flowchart outlining the conventional error correction method. In step ST30, a state transition diagram is prepared. FIG. 4 is a state transition diagram in effect where the shift register 1 has three shift stages. In FIG. 4, there exist eight states according to the bit patterns in the shift register 1. In this figure, the value in parentheses to the right of Jn (n=0-7) indicates an accumulated error of waveform data in one bit range in which a value of 1.0 is equal to a quantization step width. In a state J0, it is shown that to input "1" to the shift register 1 causes transition to a state J1. Now a case is assumed in which a loop is formed by starting from the state J0 and returning to that state through any route. This is step ST31 in FIG. 3. For example, a route EQU J0.BECAUSE.J1.fwdarw.J2.fwdarw.J4.fwdarw.J0
may be taken. As to this route, errors included in the waveform data 11c of one bit range are accumulated. The resulting accumulated value is 1.05, which exceeds the quantization step width (1.0=quantization step width). So each of the states along the above-described route is tagged with a note saying "accumulated error present" (steps ST32 and ST33). Then another typical route EQU J0.fwdarw.J1.fwdarw.J3.fwdarw.J6.fwdarw.J4.fwdarw.J0
may be taken. In this case, the accumulated value of errors is 0.0, which does not exceed the quantization step width. So each of the states along the route is tagged with a note saying "no correction needed" (step ST34). The process from step ST31 to step ST34 is repeated until every branch (a branch is a path that connects two states) is passed at least once. Whether every branch is passed at least once or not is judged in step ST35.
When every branch has been passed at least once, there may remain states with a note "accumulated error present" attached thereto. In the example above, states J2 and J5 remain noted for having an accumulated error each. In Step ST36, the states to be corrected are suitably selected to correct the waveform data 11c corresponding to these states. Then each route whose accumulated value of errors exceeds the quantization step width is checked again. Steps ST36 and ST37 are repeated until the accumulated error value falls within the quantization step width. A three-stage shift register has been used in the example above for the purpose of explanation. In practice, the number of stages of the shift register may be much larger because of the need to consider the degree of inters interference. The number of states involved is 2.sup.M where M is the number of stages. This poses quite a challenge in verifying all the branches involved.
Since waveform data has been conventionally corrected as described above, there are no definite criteria for making the correction in step ST36 of FIG. 3. Errors can only be minimized through the trial and error approach. Also, there are no criteria for selecting a route in step ST31. This has made it necessary for redundant routes to be selected many times before every branch has been passed at least once.